Embodiments of the inventive concept relate generally to methods of designing semiconductor device layouts, as well as design systems used to design semiconductor device layouts. More particularly, embodiments of the inventive concept relate to optimizing methods for integrated circuits and related components.
Contemporary semiconductor devices are amazingly complex. A myriad of integrated circuits and related components must be carefully fabricated among multiple material layers. Many different processes must be used in relation to many different types of materials in order to ultimately fabricate a semiconductor device.
Given the great complexity of contemporary semiconductor devices, a considerable amount of design consideration and simulation must be carried out before a semiconductor device is ready for mass fabrication. The design and simulation of semiconductor devices is actually becoming more and more difficult as the minimum feature size(s) defining components and spacing between component continue to shrink. Furthermore, the shrinking of minimum feature size(s) has significant performance implications for certain components and circuitry.
Accordingly, the software and hardware tools (hereafter, collectively or individually “tools”) used to design, simulate and/or optimize integrated circuits that will be included in a semiconductor device have become increasingly sophisticated. These tools usually receive a conceptual or high-level circuit design (hereafter, a “schematic circuit design”) from a team of circuit designers. A schematic circuit design, wholly or in part, conceptually represents the components and component interconnections used to implement the functionality of a particular semiconductor integrated circuit. Ultimately, each component and component interconnection represented in a schematic circuit design will be physically fabricated from one or more patterned material layers including conductive material layers, semi-conductive material layers, insulating material layers, etc.
Accordingly, a schematic circuit design must be transformed into a semiconductor design layout. Instead of being conceptual in nature and directed to the ultimate functionality of a desired integrated circuit like the schematic circuit design, a “layout” defines the physical dimensions (e.g., vertical and horizontal) of material layers in the semiconductor device. Thus, the layout of the semiconductor device exactly defines during fabrication (e.g.,) the disposition, etching, patterning, masking and/or marking of the constituent material layers.
The various parts, and interrelationship between respective parts, of a layout are geometrically governed in their layout definition by a set of rules collectively or individually referred to as a “design rule.” A design rule may be used to establish minimum component spacing, maximum feature sizes, minimum feature sizes, minimum pattern widths, minimum pattern separations, etc. The physical implementations controlled by a design rule have very real implication for the respective performance characteristics of components and circuits.
To meet the ever increasing demand for low-cost, high-density semiconductor devices, extremely fine patterning technologies are currently used to fabricate semiconductor devices. In certain instances, these fine-patterning technologies make it very difficult to functionally optimize the performance of various components and circuits included in a schematic circuit design when the schematic circuit design is transformed into a corresponding layout. Accordingly, improved layout design methods and design systems are required to fully realize the performance capabilities of contemporary semiconductor devices.